This invention relates to data buses, and particularly to controls for slave devices on data buses used in integrated circuit chips and the like.
Data buses are used in integrated circuits (ICs) to transfer data between points in the IC. Usually, the data bus couples one or more master devices, such as user-controlled microprocessors, to one or more slave devices that control peripheral devices, such as memories or the like. To avoid overlapping data messages that may lead to error in data transmission between the master and slave devices, it is common to employ an arbiter to arbitrate message traffic on the bus. One such bus design is an Advanced High-performance Bus (AHB) from ARM Limited of Cambridge, England. The AHB bus design is a form of an Advanced Microcontroller Bus Architecture (AMBA) bus. The AHB bus provides high performance, high clock frequency transfer between multiple bus master devices and multiple bus slave devices. The AHB bus is particularly useful in integrated circuit chips, including single chip processors, to couple processors to on-chip memories and off-chip external memory interfaces.
In many bus designs, including the AHB bus, if the peripheral device driven by the slave device is or becomes shut down, it is necessary to re-initialize the slave device before it can honor requests from a master device. However, the slave device can not handle requests while it resets or re-initializes. In the past, it was common to operate the slave device to stall the bus for some predetermined time period, and then release the bus for access by the master devices in accordance with the arbiter""s protocol. The stall initiated by the resetting slave usually stalled the entire bus system, halting traffic on the bus until the time period expired. If the time period was not long enough to permit the slave device to completely re-initialize, improper decoding of requests by the re-initializing slave device. If the time period was too long, time was lost as the master devices waited the extra time before issuing commands.
The present invention is directed to monitoring the slave device""s behavior to bus transactions so that the slave device can either stall or split transactions, depending on the type of transaction, in the event it is in a shut down or initializing state.
In one embodiment, a slave device receives commands from a master device for execution on a first-in, first-out basis. A status register is responsive to a command queue to provide a COMMAND_STATUS_FULL signal when the command queue is filled. A configuration register is responsive a shut down state (including initializing) of the slave device or its associated peripheral device to provide a SHUT_DOWN signal. A bus control is responsive to the command and to the COMMAND_STATUS_FULL or SHUT_DOWN signal to operate the data bus to a predetermined mode based on the command.
In preferred embodiments, an OR gate is coupled to the status register and the configuration register to provide a COMMAND_QUEUE_FULL signal to the bus control. The bus control is responsive to the COMMAND_QUEUE_FULL signal and the command to idle the data bus and deny the requesting master device access to the data bus if the command is for a non-locked transfer, or to stall the data bus if the command is for a locked transfer request.